ST STM32F301 6 Series Reference Manual page 205

RM0366
12.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible
to select among the following sampling time values:
• SMP = 000: 1.5 ADC clock cycles
•
SMP = 001: 2.5 ADC clock cycles
• SMP = 010: 4.5 ADC clock cycles
•
SMP = 011: 7.5 ADC clock cycles
• SMP = 100: 19.5 ADC clock cycles
•
SMP = 101: 61.5 ADC clock cycles
•
SMP = 110: 181.5 ADC clock cycles
•
SMP = 111: 601.5 ADC clock cycles
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 ADC clock cycles
Example:
With F
Tconv = (1.5 + 12.5) ADC clock cycles = 14 ADC clock cycles = 0.194 µs (for fast
channels)
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).
Constraints on the sampling time for fast and slow channels
For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC charateristics section of the datasheets.
12.3.13 Single conversion mode (CONT=0)
In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
•
Setting the ADSTART bit in the ADCx_CR register (for a regular channel)
•
Setting the JADSTART bit in the ADCx_CR register (for an injected channel)
•
External hardware trigger event (for a regular or injected channel)
Inside the regular sequence, after each conversion is complete:
•
The converted data are stored into the 16-bit ADCx_DR register
•
The EOC (end of regular conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
= 72 MHz and a sampling time of 1.5 ADC clock cycles:
ADC_CLK
RM0366 Rev 5
Analog-to-digital converters (ADC)
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