ST STM32F301 6 Series Reference Manual page 552

General-purpose timers (TIM15/TIM16/TIM17)
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x t
DTG[7:5] = 10x => DT = (64+DTG[5:0]) x t
DTG[7:5] = 110 => DT = (32+DTG[4:0]) x t
DTG[7:5] = 111 => DT = (32+DTG[4:0]) x t
Example if t
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
19.5.17 TIM15 DMA control register (TIM15_DCR)
Address offset: 0x48
Reset value: 0x0000
15 14 13
Res. Res. Res.
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
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register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
has been written, their content is frozen until the next reset.
= 125 ns (8 MHz), dead-time possible values are:
DTS
(LOCK bits in TIMx_BDTR register).
12 11 10 9
DBL[4:0]
rw rw rw rw
with t = t
dtg dtg
with t
dtg
with t
dtg
with t
dtg
8 7 6
Res. Res.
rw
RM0366 Rev 5
DTS
= 2 x t
dtg DTS
= 8 x t
dtg DTS
= 16 x t
dtg DTS
5 4 3 2
Res. DBA[4:0]
rw rw rw
RM0366
1 0
rw rw