ST STM32F301 6 Series Reference Manual page 511

RM0366
Figure 214. Output stage of capture/compare channel (channel 1)
OCREF_CLR
OC1REF
CNT>CCR1
Output
mode
CNT=CCR1
controller
OC2REF
OC1CE OC1M[3:0]
TIMx_CCMR1
Figure 215. Output stage of capture/compare channel (channel 2 for TIM15)
OCREF_CLR
CNT > CCR2
CNT = CCR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
19.4.6 Input capture mode
In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
To the master mode
controller
OC1REFC
Output Dead-time
selector generator
DTG[7:0]
TIMx_BDTR
OC2REF
Output
mode
controller
OC1REF
OC2CE OC2M[3:0]
TIMx_CCMR1
General-purpose timers (TIM15/TIM16/TIM17)
'0'
x0
01
OC1_DT
11
OC1N_DT
11
10
'0'
0x
CC1NE CC1E
TIMx_CCER
To the master
mode controller
OC2REFC
'0'
0
Output
1
selector
CC2E
TIMx_CCER
RM0366 Rev 5
0
Output
enable
1
circuit
CC1P
TIM1_CCER
0
Output
enable
1
circuit
CC1E TIMx_CCER
CC1NE
MOE OSSI OSSR
CC1NP
TIMx_CCER TIMx_BDTR
OIS1 OIS1N TIMx_CR2
0
Output
enable
1
circuit
CC2P
CC2E TIMx_CCER
TIMx_CCER
OIS2 TIMx_CR2
OC1
OC1N
MS31090V3
OC2
MS31091V3
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