ST STM32F301 6 Series Reference Manual page 686

Inter-integrated circuit interface (I2C)
25.4.13 SMBus I2C_TIMEOUTR register configuration examples
The following tables provide examples of settings to reach desired t
t
LOW:MEXT
f
I2CCLK
8 MHz
16 MHz
48 MHz
Table 94. TIMEOUTB[11:0] for maximum t
f
I2CCLK
8 MHz
16 MHz
48 MHz
f
I2CCLK
8 MHz
16 MHz
48 MHz
25.4.14 SMBus target mode
In addition to I2C target transfer management (refer to
section provides extra software flowcharts to support SMBus.
SMBus target transmitter
When using the I2C peripheral in SMBus mode, set the SBC bit to enable the PEC
transmission at the end of the programmed number of data bytes. When the PECBYTE bit
is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In
that case, the total number of TXIS interrupts is NBYTES[7:0] - 1, and the content of the
I2C_PECR register is automatically transmitted if the controller requests an extra byte after
the transfer of the NBYTES[7:0] - 1 data bytes.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.
686/874
, and t timings at different f
IDLE
Table 93. TIMEOUTA[11:0] for maximum t
TIMEOUTA[11:0]
0x61
0xC3
0x249
TIMEOUTB[11:0]
0x1F
0x3F
0xBB
Table 95. TIMEOUTA[11:0] for maximum t
TIMEOUTA[11:0]
0x63
0xC7
0x257
frequencies.
I2CCLK
TIDLE TIMEOUTEN
0 1
0 1
0 1
LOW:SEXT
TEXTEN
1
1
1
TIDLE TIMEOUTEN
1 1
1 1
1 1
Section 25.4.8: I2C target
RM0366 Rev 5
, t
TIMEOUT LOW:SEXT
of 25 ms
TIMEOUT
t
TIMEOUT
98 x 2048 x 125 ns = 25 ms
196 x 2048 x 62.5 ns = 25 ms
586 x 2048 x 20.08 ns = 25 ms
and t of 8 ms
LOW:MEXT
t
LOW:SEXT
t
LOW:MEXT
32 x 2048 x 125 ns = 8 ms
64 x 2048 x 62.5 ns = 8 ms
188 x 2048 x 20.08 ns = 8 ms
of 50 µs
IDLE
t
IDLE
100 x 4 x 125 ns = 50 µs
200 x 4 x 62.5 ns = 50 µs
600 x 4 x 20.08 ns = 50 µs
RM0366
,
mode), this