ST STM32F301 6 Series Reference Manual page 716

Universal synchronous/asynchronous receiver transmitter (USART/UART)
TX
RX
RTS/
DE
CTS
Transmitter
1. For details on coding USARTDIV in the USART_BRR register, refer to
generation.
2. f can be f
CK
716/874
Figure 276. USART block diagram
PRDATA
Write
(CPU or DMA)
Transmit shift register
IrDA
SIR
Transmit data register
ENDEC
block
USART_CR3 register
USART_CR2 register
Hardware
flow
controller
Transmit
control
USART_CR1 register
USART
interrupt
control
/USARTDIV or 2/USARTDIV
(depending on the
clock oversampling mode)
(Note 1)
f
CK
, f , f , f .
LSE HSI PCLK SYS
Read
(CPU or DMA)
Receive shift register
Receive data register
(TDR)
USART_GTPR register
GT PSC
USART_CR1 register
Wakeup
unit
USART_BRR register
TE
RE
(Note 2)
Conventional baud rate generator
RM0366 Rev 5
DR (data register)
(RDR)
CK control
USART_CR2 register
Receiver
clock
Receiver
control
USART_ISR register
Transmitter
rate controller
BRR[15:0]
Receiver rate
controller
Section 26.5.4: USART baud rate
RM0366
PWDATA
CK
MS19821V8