ST STM32F301 6 Series Reference Manual page 666

Inter-integrated circuit interface (I2C)
Target receiver
The RXNE bit of the I2C_ISR register is set when the I2C_RXDR is full, which generates an
interrupt if the RXIE bit of the I2C_CR1 register is set. RXNE is cleared when I2C_RXDR is
read.
When STOP condition is received and the STOPIE bit of the I2C_CR1 register is set, the
STOPF flag in the I2C_ISR register is set and an interrupt is generated.
Figure 256. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0
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Target reception
Target initialization
No
I2C_ISR.ADDR
=1?
Yes
Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF
I2C_ISR.RXNE
=1?
Yes
Write I2C_RXDR.RXDATA
RM0366 Rev 5
SCL
stretched
No
RM0366
MSv19855V3