ST STM32F301 6 Series Reference Manual page 424

Advanced-control timer (TIM1)
Offset Register
TIM1_CNT
0x24
Reset value 0
TIM1_PSC
0x28
Reset value
TIM1_ARR
0x2C
Reset value
TIM1_RCR
0x30
Reset value
TIM1_CCR1
0x34
Reset value
TIM1_CCR2
0x38
Reset value
TIM1_CCR3
0x3C
Reset value
TIM1_CCR4
0x40
Reset value
TIM1_BDTR
0x44
Reset value
TIM1_DCR
0x48
Reset value
TIM1_DMAR
0x4C
Reset value 0
TIM1_OR
0x50
Reset value
424/874
Table 62. TIM1 register map and reset values (continued)
BK2F[3:0]
0 0 0
0 0 0 0 0 0 0 0
0 0
0 0
1 1
0 0
0 0
0 0
0 0
0 0
BKF[3:0]
0 0 0 0 0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0 0
RM0366 Rev 5
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1 1
REP[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
LOC
K
[1:0]
0 0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
0 0 0 0 0 0 0 0 0
RM0366
0 0 0 0 0
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
DT[7:0]
0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0