ST STM32F301 6 Series Reference Manual page 468

General-purpose timer (TIM2)
In the next example (refer to
master and starts from 0. TIM2 is the slave and starts from 0xE7. The prescaler ratio is the
same for both timers. TIM2 stops when TIM1 is disabled by writing '0 to the CEN bit in the
TIM1_CR1 register:
1. Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
2. Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register).
3. Configure TIM2 to get the input trigger from TIM1 (TS=000 in the TIM2_SMCR
register).
4. Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).
5. Reset TIM1 by writing '1 in UG bit (TIM1_EGR register).
6. Reset TIM2 by writing '1 in UG bit (TIM2_EGR register).
7. Initialize TIM2 to 0xE7 by writing '0xE7' in the TIM2 counter (TIM2_CNTL).
8. Enable TIM2 by writing '1 in the CEN bit (TIM2_CR1 register).
9. Start TIM1 by writing '1 in the CEN bit (TIM1_CR1 register).
10. Stop TIM1 by writing '0 in the CEN bit (TIM1_CR1 register).
TIM1-CEN=CNT_EN
TIM1-CNT_INIT
TIM2-CNT_INIT
TIM2-write CNT
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to
Figure 192
non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write '0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (f
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Figure
Figure 195. Gating TIM2 with Enable of TIM1
CK_INT
TIM1-CNT
75
TIM2-CNT
AB
TIM2-TIF
for connections. Timer 2 starts counting from its current value (which can be
195), we synchronize TIM1 and TIM2. TIM1 is the
00
00 E7
Write TIF = 0
RM0366 Rev 5
01 02
E8 E9
= f
CK_CNT CK_INT
RM0366
MS32696V1
/3).