ST STM32F301 6 Series Reference Manual page 198

Analog-to-digital converters (ADC)
Clock ratio constraint between ADC clock and AHB clock
There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
•
F
HCLK
• F
HCLK
with lower resolutions)
•
F
HCLK
12.3.4 ADC1 connectivity
ADC1_IN1
ADC1_IN2
ADC1_IN3
ADC1_IN4
ADC1_IN5
ADC1_IN6
ADC1_IN7
ADC1_IN8
ADC1_IN9
ADC1_IN10
ADC1_IN11
ADC1_IN12
ADC1_IN13
ADC1_IN14
ADC1_IN15
12.3.5 Slave AHB interface
The ADCs implement an AHB slave port for control/status register and data access. The
features of the AHB interface are listed below:
•
Word (32-bit) accesses
• Single cycle response
•
Response to all read/write accesses to the registers with zero wait states.
The AHB slave interface does not support split/retry requests, and never generates AHB
errors.
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>= F / 4 if the resolution of all channels are 12-bit or 10-bit
ADC
>= F / 3 if there are some channels with resolutions equal to 8-bit (and none
ADC
>= F / 2 if there are some channels with resolutions equal to 6-bit
ADC
Figure 26. ADC1 connectivity
STM32F3xx
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
TS V
V
REF-
V
V /2
V
BAT
V
REF-
V
V
V
V
REFINT
REF-
V
REF-
RM0366 Rev 5
ADC1
Channel Selection
[1]
INP
[1]
fast channel
INN
[2]
INP
[2]
fast channel
INN
[3]
INP
[3]
fast channel
INN
[4]
INP
[4]
fast channel
INN
[5]
INP
[5] fast channel
INN
[6]
INP
[6] slow channel
INN
[7]
INP
[7]
slow channel
INN
[8]
INP
[8] slow channel
INN
[9]
INP
[9]
slow channel
INN
[10]
INP
[10] slow channel
INN
[11]
INP
[11] slow channel
INN
[12]
INP
[12] slow channel
INN
[13]
INP
[13]
slow channel
INN
[14]
INP
[14]
slow channel
INN
[15]
INP
[15] slow channel
INN
[16]
INP
[16]
slow channel
INN
[17]
INP
[17]
slow channel
INN
[18]
INP
[18]
slow channel
INN
V
REF+
V
INP
SAR
V ADC1
INN
V
REF-
Single-ended
Mode
MS32691V4
RM0366