ST STM32F301 6 Series Reference Manual page 252

Analog-to-digital converters (ADC)
Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified by the
AWD1CH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 21 JQM: JSQR queue mode
This bit is set and cleared by software.
It defines how an empty Queue is managed.
0: JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
1: JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware
triggers of the injected sequence are both internally disabled just after the completion of the last valid
injected sequence.
Refer to Section 12.3.21: Queue of context for injected conversions
Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected
conversion is ongoing).
Bit 20 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels
of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected
conversion is ongoing).
Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted in
discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 16 DISCEN: Discontinuous mode for regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.
0: Discontinuous mode for regular channels disabled
1: Discontinuous mode for regular channels enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 15 Reserved, must be kept at reset value.
252/874 RM0366 Rev 5
for more information.
RM0366