ST STM32F301 6 Series Reference Manual page 815

RM0366
PCM standard
For the PCM standard, there is no need to use channel-side information. The two PCM
modes (short and long frame) are available and configurable using the PCMSYNC bit in
SPIx_I2SCFGR register.
In PCM mode, the output signals (WS, SD) are sampled on the rising edge of CK signal.
The input signals (WS, SD) are captured on the falling edge of CK.
Note that CK and WS are configured as output in MASTER mode.
short frame
For long frame synchronization, the WS signal assertion time is fixed to 13 bits in master
mode.
For short frame synchronization, the WS synchronization signal is only one cycle long.
Figure 335. PCM standard waveforms (16-bit extended to 32-bit packet frame)
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.
27.7.4 Start-up description
TheFigure 336
SPI/I2S is enabled (via I2SE bit). It shows as well the effect of CKPOL on the generated
signals.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
Figure 334. PCM standard waveforms (16-bit)
CK
WS
WS
long frame
SD
MSB
CK
WS
short frame
Up to 13-bits
WS
long frame
SD
MSB
shows how the serial interface is handled in MASTER mode, when the
13-bits
LSB MSB
16 bits
LSB
RM0366 Rev 5
MS30106V1
MS30107V1
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