ST STM32F301 6 Series Reference Manual page 48

Embedded flash memory
Prefetch buffer
The prefetch buffer is 2 blocks wide where each block consists of 8 bytes. The prefetch
blocks are direct-mapped. A block can be completely replaced on a single read to the flash
memory as the size of the block matches the bandwidth of the flash memory.
The implementation of this prefetch buffer makes a faster CPU execution possible as the
CPU fetches one word at a time with the next word readily available in the prefetch buffer.
This implies that the acceleration ratio is in the order of 2, assuming that the code is aligned
at a 64-bit boundary for the jumps.
Prefetch controller
The prefetch controller decides to access the flash memory depending on the available
space in the prefetch buffer. The Controller initiates a read request when there is at least
one block free in the prefetch buffer.
After reset, the state of the prefetch buffer is on. The prefetch buffer must be switched on/off
only when no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The
prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.
Note: The prefetch buffer must be kept on (FLASH_ACR[4]='1') when using a prescaler different
from 1 on the AHB clock.
If there is not any high frequency clock available in the system, flash memory accesses can
be made on a half cycle of HCLK (AHB clock). This mode can be selected by setting a
control bit in the Flash access control register.
Half-cycle access cannot be used when there is a prescaler different from 1 on the AHB
clock.
Access latency
To maintain the control signals to read the flash memory, the ratio of the prefetch controller
clock period to the access time of the flash memory has to be programmed in the Flash
access control register with the LATENCY[2:0] bits. This value gives the number of cycles
needed to maintain the control signals of the flash memory and correctly read the required
data. After reset, the value is zero and only one cycle without additional wait states is
required to access the flash memory.
DCode interface
The DCode interface consists of a simple AHB interface on the CPU side and a request
generator to the Arbiter of the Flash access controller. The DCode accesses have priority
over prefetch accesses. This interface uses the Access Time Tuner block of the prefetch
buffer.
Flash Access controller
Mainly, this block is a simple arbiter between the read requests of the prefetch/ICode and
DCode interfaces.
DCode interface requests have priority over other requests.
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