ST STM32F301 6 Series Reference Manual page 121

RM0366
Bit 18 GPIOBRST: I/O port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 17 GPIOARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bits 16:0 Reserved, must be kept at reset value.
7.4.12 Clock configuration register 2 (RCC_CFGR2)
Address: 0x2C
Reset value: 0x0000 0000
Access: no wait states, word, half-word, and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:4 ADC1PRES: ADC1 prescaler
Set and reset by software to control PLL clock to ADC1 division factor.
0xxxx: ADC1 clock disabled, ADC1 can use AHB clock
10000: PLL clock divided by 1
10001: PLL clock divided by 2
10010: PLL clock divided by 4
10011: PLL clock divided by 6
10100: PLL clock divided by 8
10101: PLL clock divided by 10
10110: PLL clock divided by 12
10111: PLL clock divided by 16
11000: PLL clock divided by 32
11001: PLL clock divided by 64
11010: PLL clock divided by 128
11011: PLL clock divided by 256
others: PLL clock divided by 256
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
ADC1PRES[4:0]
rw rw rw
RM0366 Rev 5
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PREDIV[3:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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