ST STM32F301 6 Series Reference Manual page 849

RM0366
A(3:2)
10 Write
11 Read/Write
28.8.6 SW-AP registers
Access to these registers is initiated when APnDP=1
There are many AP Registers (see AHB-AP) addressed as the combination of:
•
The shifted value A[3:2]
• The current value of the DP SELECT register
28.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP
Features:
•
System access is independent of the processor status.
•
Either SW-DP or JTAG-DP accesses AHB-AP.
•
The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
•
Bitband transactions are supported.
•
AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
d)
e)
The AHB-AP of the Cortex
Table 120. SW-DP registers (continued)
CTRLSEL bit
R/W of SELECT
register
-
-
Bits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register
Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP.
®
-M4F includes 9 x 32-bits registers:
Register
The purpose is to select the current access
SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
READ
transaction).
BUFFER
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
RM0366 Rev 5
Debug support (DBG)
Notes
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