ST STM32F301 6 Series Reference Manual page 844

Debug support (DBG)
Bits 31:16 REV_ID[15:0] Revision identifier
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DEV_ID[11:0]: Device identifier
28.6.2 Boundary scan TAP
JTAG ID code
The TAP of the STM32F3xx BSC (boundary scan) integrates a JTAG ID code equal to
0x06432041.
28.6.3 Cortex
The TAP of the Cortex
one and has not been modified. This code is only accessible by the JTAG Debug Port.
This code is 0x4BA00477 (corresponds to Cortex
Arm documentation).
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
28.6.4 Cortex
The Cortex
mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
28.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
(TRM), for references, please see
IR(3:0)
1111
1110
844/874
This field indicates the revision of the device. For example, it is read as 0x1000 for Revision
1.
This field indicates the device and its revision.
The device ID is 0x439 for STM32F301x6x8 devices.
®
-M4F TAP
®
-M4F integrates a JTAG ID code. This ID code is the Arm
®
-M4F JEDEC-106 ID code
®
-M4F integrates a JEDEC-106 ID code. It is located in the 4KB ROM table
Table 115. JTAG debug port data registers
Data register
BYPASS
[1 bit]
IDCODE ID CODE
[32 bits] 0x3BA00477 (Cortex
®
-M4F r0p1, see
®
-M4Fr0p1 Technical Reference Manual
Section 28.2: Reference Arm
®
-M4F r0p1 ID Code)
RM0366 Rev 5
Section 28.2: Reference
documentation).
Details
RM0366
®
default