ST STM32F301 6 Series Reference Manual page 109

RM0366
7.4.4 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
USART1
Res.
RST Res.
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG, Comparators and operational amplifiers reset
Set and cleared by software.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
TIM1
Res. Res.
Res RST
rw
0: No effect
1: Reset TIM17 timer
0: No effect
1: Reset TIM16 timer
0: No effect
1: Reset TIM15 timer
0: No effect
1: Reset USART1
0: No effect
1: Reset TIM1 timer
0: No effect
1: Reset SYSCFG, COMP, and OPAMP
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0366 Rev 5
Reset and clock control (RCC)
21 20 19 18
TIM17
Res. Res. Res.
RST
rw
5 4 3 2
Res. Res. Res. Res.
17 16
TIM16 TIM15
RST RST
rw rw
1 0
SYS
Res. CFG
RST
rw
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