ST STM32F301 6 Series Reference Manual page 444

General-purpose timer (TIM2)
f CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock =
CK_CNT =CK_PSC
Counter register
18.3.4 Capture/Compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
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Figure 173. Control circuit in external clock mode 2
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RM0366 Rev 5
RM0366
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MSv33111V3