ST STM32F301 6 Series Reference Manual page 725

RM0366
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock
Figure 282).
Depending on the application:
•
Select oversampling by 8 (OVER8=1) to achieve higher speed (up to f
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 26.5.5: Tolerance of the USART receiver to clock deviation on page
•
Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum f
f is the clock source frequency.
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Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
• The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
•
A single sample in the center of the received bit
Depending on the application:
–
–
When noise is detected in a frame:
•
The NF bit is set at the rising edge of the RXNE bit.
•
The invalid data is transferred from the Shift register to the USART_RDR register.
•
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3
register.
The NF bit is reset by setting NFCF bit in ICR register.
Note: Oversampling by 8 is not available in LIN, smartcard and IrDA modes. In those modes, the
OVER8 bit is forced to '0' by hardware.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
select the three samples' majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 100) because this indicates that a glitch occurred during the sampling.
select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver's tolerance to clock deviations (see
Tolerance of the USART receiver to clock deviation on page
NF bit will never be set.
RM0366 Rev 5
(Figure 281 and
/8). In this
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730)
/16 where
CK
Section 26.5.5:
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