ST STM32F301 6 Series Reference Manual page 423

RM0366
17.4.27 TIM1 register map
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
Offset Register
TIM1_CR1
0x00
Reset value
TIM1_CR2
0x04
Reset value
TIM1_SMCR
0x08
Reset value
TIM1_DIER
0x0C
Reset value
TIM1_SR
0x10
Reset value
TIM1_EGR
0x14
Reset value
TIM1_CCMR1
Input Capture
mode
Reset value
0x18
TIM1_CCMR1
Output
Compare mode
Reset value
TIM1_CCMR2
Input Capture
mode
Reset value
0x1C
TIM1_CCMR2
Output
Compare mode
Reset value
TIM1_CCER
0x20
Reset value
Table 62. TIM1 register map and reset values
MMS2[3:0]
0 0 0
0
0
0
RM0366 Rev 5
0 0 0 0 0 0
ETP
S
[1:0]
0 0 0 0 0
0 0 0
0 0 0
IC2F[3:0]
0 0 0 0
OC2M
[2:0]
0 0 0 0 0
IC4F[3:0]
0 0 0 0
OC4M
[2:0]
0 0 0 0 0
0 0 0 0 0 0
Advanced-control timer (TIM1)
CKD CMS
[1:0] [1:0]
0 0 0 0 0 0 0
MMS
[2:0]
0 0 0 0 0 0 0 0
ETF[3:0] TS[2:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0
IC2 CC2
PSC S IC1F[3:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0
CC2
OC1M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0
IC4 CC4
PSC S IC3F[3:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0
CC4
OC3M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0
0 0 0
SMS[2:0]
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
IC1 CC1
PSC S
[1:0] [1:0]
0 0 0 0
CC1
S
[1:0]
0 0 0 0
IC3 CC3
PSC S
[1:0] [1:0]
0 0 0 0
CC3
S
[1:0]
0 0 0 0
0 0 0 0
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