ST STM32F10 Series Application Note
ST STM32F10 Series Application Note

ST STM32F10 Series Application Note

Getting started hardware development
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Getting started with STM32F10xxx hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the low-density value line, low-density, medium-density value line,
medium-density, high-density, XL-density and connectivity line STM32F10xxx product
families and describes the minimum hardware resources required to develop an
STM32F10xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
Glossary
Low-density value line devices are STM32F100xx microcontrollers where the Flash
memory density ranges between 16 and 32 Kbytes.
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 64 and 128 Kbytes.
Medium-density devices are STM32F100xx, STM32F101xx, STM32F102xx and
STM32F103xx microcontrollers where the Flash memory density ranges between 64
and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the Flash
memory density ranges between 256 and 512 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
November 2011
Doc ID 13675 Rev 7
AN2586
Application note
www.st.com
1/28

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Summary of Contents for ST STM32F10 Series

  • Page 1 Flash memory density ranges between 256 and 512 Kbytes. ● XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. ● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. November 2011 Doc ID 13675 Rev 7 1/28 www.st.com...
  • Page 2: Table Of Contents

    Contents AN2586 Contents Power supplies ..........6 Introduction .
  • Page 3 AN2586 Contents Recommendations ......... 20 Printed circuit board .
  • Page 4 List of tables AN2586 List of tables Table 1. Boot modes............. 15 Table 2.
  • Page 5 AN2586 List of figures List of figures Figure 1. Power supply overview ........... . . 6 Figure 2.
  • Page 6: Power Supplies

    Power supplies AN2586 Power supplies Introduction The device requires a 2.0 V to 3.6 V operating voltage supply (V ). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the V voltage when the main V supply is powered off.
  • Page 7: Battery Backup

    AN2586 Power supplies On packages with 64 pins or less The V and V pins are not available, they are internally connected to the ADC REF+ REF- voltage supply (V ) and ground (V 1.1.2 Battery backup To retain the content of the Backup registers when V is turned off, the V pin can be connected to an optional standby voltage supplied by a battery or another source.
  • Page 8: Reset And Power Supply Supervisor

    Power supplies AN2586 Figure 2. Power supply scheme STM32F10xxx REF+ Battery 100 nF + 1 µF (note 1) 100 nF + 1 µF N × 100 nF DD 1/2/3/.../N + 1 × 10 µF REF– SS 1/2/3/.../N ai14865b 1. Optional. If a separate, external reference voltage is connected on V , the two capacitors (100 nF and REF+ 1 µF) must be connected.
  • Page 9: Programmable Voltage Detector (Pvd)

    AN2586 Power supplies 1.3.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate whether V is higher or lower than the PVD threshold.
  • Page 10: Figure 5. Reset Circuit

    Power supplies AN2586 The STM32F1xx does not require an external reset circuit to power-up correctly. Only a pull- down capacitor is recommended to improve EMS performance by protecting the device against parasitic resets. See Figure Charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption.
  • Page 11: Clocks

    AN2586 Clocks Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock (high-speed internal clock signal) ● HSE oscillator clock (high-speed external clock signal) ● PLL clock The devices have two secondary clock sources: ●...
  • Page 12: External Source (Hse Bypass)

    Clocks AN2586 2.1.1 External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to: ● 24 MHz for STM32F100xx value line devices ● 25 MHz for STM32F101xx, STM32F102xx and STM32F103xx devices ●...
  • Page 13: Lse Osc Clock

    Typical value is in the range of 5 to 6 R (resonator series resistance). To fine tune R value refer to AN2867 - Oscillator design guide for ST microcontrollers. 2.2.1 External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz.
  • Page 14: Clock Security System (Css)

    PLL used as system clock when the failure occurs, the PLL is disabled too. For details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference manuals available from the STMicroelectronics website www.st.com. 14/28 Doc ID 13675 Rev 7...
  • Page 15: Boot Configuration

    AN2586 Boot configuration Boot configuration Boot mode selection In the STM32F10xxx, three different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table Table 1. Boot modes BOOT mode selection pins Boot mode Aliasing BOOT1 BOOT0 Main Flash memory is selected as boot Main Flash memory...
  • Page 16: Embedded Boot Loader Mode

    USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For further details, please refer to AN2662. This embedded boot loader is located in the System memory and is programmed by ST during production.
  • Page 17: Debug Management

    (STM3210B-EVAL, STM3210C-EVAL, STM32100B-EVAL or STM3210E-EVAL). The Value line evaluation board (STM32100B-EVAL or STM32100E-EVAL) embeds the debug tools (ST-LINK). Consequently, it can be directly connected to the PC through a USB cable. Figure 11. Host-to-board connection SWJ debug port (serial wire and JTAG) The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP).
  • Page 18: Flexible Swj-Dp Pin Assignment

    JTAG-DP disabled and SW-DP disabled Released Table 3 shows the different possibilities to release some pins. For more details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference manuals, available from the STMicroelectronics website www.st.com. 18/28 Doc ID 13675 Rev 7...
  • Page 19: Internal Pull-Up And Pull-Down Resistors On Jtag Pins

    AN2586 Debug management 4.3.3 Internal pull-up and pull-down resistors on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops.
  • Page 20: Recommendations

    Recommendations AN2586 Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.
  • Page 21: Other Signals

    AN2586 Recommendations Figure 13. Typical layout for V pair Via to V Via to V Cap. STM32F10xxx Other signals When designing an application, the EMC performance can be improved by closely studying: ● Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands).
  • Page 22: Reference Design

    Reference design AN2586 Reference design Description The reference design shown in Figure 14, is based on the STM32F103ZE(T6), a highly ™ integrated microcontroller running at 72 MHz, that combines the new Cortex -M3 32-bit RISC CPU core with 512 Kbytes of embedded Flash memory and up to 64 Kbytes of high- speed SRAM This reference design can be tailored to any other STM32F10xxx device with different package, using the pins correspondence given in...
  • Page 23: Component References

    AN2586 Reference design Component references Table 4. Mandatory components Components name Reference Quantity Comments Microcontroller STM32F103ZE(T6) 144-pin package Ceramic capacitors (decoupling Capacitors 100 nF capacitors) Ceramic capacitor (decoupling Capacitor 10 µF capacitor) Table 5. Optional components Components name Reference Quantity Comments Pull-up and pull-down for JTAG and Boot Resistor...
  • Page 24: Figure 14. Stm32F103Ze(T6) Microcontroller Reference Schematic

    Reference design AN2586 Figure 14. STM32F103ZE(T6) microcontroller reference schematic 1. If no external battery is used in the application, it is recommended to connect V externally to V 2. To be able to reset the device from the tools this resistor has to be kept. 24/28 Doc ID 13675 Rev 7...
  • Page 25: Table 6. Reference Connection For All Packages

    AN2586 Reference design Table 6. Reference connection for all packages Pin numbers for Pin numbers for Pin numbers for LQFP packages BGA packages VFQFPN package Pin name 144 pins 100 pins 64 pins 48 pins 144 pins 100 pins 36 pins OSC_IN OSC_OUT PC15-...
  • Page 26 Reference design AN2586 Table 6. Reference connection for all packages (continued) Pin numbers for Pin numbers for Pin numbers for LQFP packages BGA packages VFQFPN package Pin name 144 pins 100 pins 64 pins 48 pins 144 pins 100 pins 36 pins DD_9 DD_10...
  • Page 27: Revision History

    AN2586 Revision history Revision history Table 7. Document revision history Date Revision Changes 12-Jul-2007 Initial release. Application note also applicable to High-density devices. Figure 1: Power supply overview, Figure 2: Power supply scheme Figure 6: Clock overview updated. 23-May-2008 Low-speed internal RC frequency modified in Section 2: Clocks on page 11.
  • Page 28 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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