ST STM32F301 6 Series Reference Manual page 113

RM0366
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
Bit 1 Reserved, must be kept at reset value.
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word, and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29
Res. Res. Res. Res.
15 14 13
USART
Res. Res.
1EN Res.
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: TIM16 timer clock disabled
1: TIM16 timer clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 timer clock disabled
1: TIM15 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
0: DMA1 clock disabled
1: DMA1 clock enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM1
Res. Res.
EN
rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res. Res.
RM0366 Rev 5
Reset and clock control (RCC)
21 20 19 18
TIM17
Res. Res.
EN
rw
5 4 3 2
Res. Res. Res.
17 16
TIM16 TIM15
EN EN
rw rw
1 0
SYS
Res.
CFGEN
rw
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