ST STM32F301 6 Series Reference Manual page 197

RM0366
The input clock of the two ADCs (master and slave) can be selected between two different
clock sources (see
a)
b)
Note: Software can use option b) by writing CKMODE[1:0]=01 only if the AHB prescaler of the
RCC is set to 1 (the duty cycle of the AHB clock must be 50% in this configuration).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits
ADCxPRES[4:0] in register RCC_CFGR2 (Refer to
(RCC)).
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
1. Refer to the RCC section to see how HCLK can be generated.
Figure 25: ADC clock
The ADC clock can be a specific clock source, named "ADCxy_CK (xy=12 or 34)
which is independent and asynchronous with the AHB clock".
It can be configured in the RCC to deliver up to 72 MHz (PLL output). Refer to
RCC Section for more information on generating ADC12_CK.
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
reset.
The ADC clock can be derived from the AHB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider
factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
different from "00".
Figure 25. ADC clock scheme
RCC
(Reset and clock
controller)
scheme):
Section 7: Reset and clock control
ADC1
HCLK
AHB
interface
Bits CKMODE[1:0]
of ADC12_CCR
/1 or /2
or /4
ADC1_CK
RM0366 Rev 5
Analog-to-digital converters (ADC)
Others
Analog ADC1
(master)
00
Bits CKMODE[1:0]
of ADC1_CCR
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