ST STM32F301 6 Series Reference Manual page 196

Analog-to-digital converters (ADC)
12.3.2 Pins and internal signals
Internal signal name
EXT[15:0]
JEXT[15:0]
ADC1_AWDx_OUT
V
TS
V
REFINT
V
BAT
Name
VREF+
VDDA
VREF-
VSSA
V [18:1]
INP
V [18:1]
INN
ADCx_IN15:1 External analog input signals
1. In F301xx devices the VREF+ and VDDA are connected internally.
12.3.3 Clocks
Dual clock domain architecture
The dual clock-domain architecture means that each ADC clock is independent from the
AHB bus clock.
196/874
Table 30. ADC internal signals
Signal
type
Up to 16 external trigger inputs for the regular conversions (can
be connected to on-chip timers).
Inputs
These inputs are shared between the ADC master and the ADC
slave.
Up to 16 external trigger inputs for the injected conversions (can
be connected to on-chip timers).
Inputs
These inputs are shared between the ADC master and the ADC
slave.
Internal analog watchdog output signal connected to on-chip
Output
timers. (x = Analog watchdog number 1,2,3)
Input Output voltage from internal temperature sensor
Input Output voltage from internal reference voltage
Input
External battery voltage supply
supply
Table 31. ADC pins
Signal type
Input, analog reference
positive
Input, analog supply
Input, analog reference
negative
Input, analog supply ground
Positive input analog
channels for each ADC
Negative input analog
channels for each ADC
RM0366 Rev 5
Description
Comments
The higher/positive reference voltage for the ADC,
(1)
1.8 V ≤ V ≤ V
REF+ DDA
Analog power supply equal V
1.8V ≤ V ≤ 3.6 V
DDA
The lower/negative reference voltage for the ADC,
V = V
REF- SSA
Ground for analog power supply equal to V
Connected either to external channels: ADC_INi or
internal channels.
Connected to V or external channels: ADC_INi-1
REF-
Up to 15 analog input channels (x = ADC number =
1):
– 5 fast channels
– 10 slow channels
RM0366
:
DDA
SS