ST STM32F301 6 Series Reference Manual page 235

RM0366
Figure 61. AUTODLY=1, regular continuous conversions interrupted by injected conversions
(1)
ADSTART
ADC
CH1
RDY
state
regular
EOC
EOS
ADC_DR read access
ADC_DR
Injected
trigger
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
(1)
ADSTART
ADC state RDY CH1
regular
EOC
EOS
ADC_DR read access
ADC_DR
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6
CH2
DLY
regular
DLY (CH1)
D1
by h/w
Figure 62. AUTODLY=1 in auto- injected mode (JAUTO=1)
DLY (CH1) CH2
regular injected
D1
by h/w
DLY CH5 CH6
injected injected
DLY (CH2)
D2
No delay
CH5 CH6 DLY (inj)
injected
D2
RM0366 Rev 5
Analog-to-digital converters (ADC)
DLY CH3
regular
Ignored
DLY (inj)
D5
D6
Indicative timings
DLY(CH2) CH3
regular
D5
D6
Indicative timings
DLY CH1
regular
DLY (CH3)
D3
MS31023V2
DLY CH1
regular
D3
MS31024V2
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