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ST STM32F301 6 Series Reference Manual page 853

Advanced arm-based 32-bit mcus

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RM0366
Address
@E0000FB0 ITM lock access
@E0000E80
@E0000E40
@E0000E00
@E0000000-
E000007C
Example of configuration
To output a simple value to the TPIU:
Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to
Section 28.15.6: TRACE pin assignment
configuration
Write 0xC5ACCE55 to the ITM Lock Access Register to unlock the write access to the
ITM registers
Write 0x00010005 to the ITM Trace Control Register to enable the ITM with Sync
enabled and an ATB ID different from 0x00
Write 0x1 to the ITM Trace Enable Register to enable the Stimulus Port 0
Write 0x1 to the ITM Trace Privilege Register to unmask stimulus ports 7:0
Write the value to output in the Stimulus Port Register 0: this can be done by software
(using a printf function)
Table 123. Main ITM registers
Register
Write 0xC5ACCE55 to unlock Write Access to the other ITM
registers
Bits 31-24 = Always 0
Bits 23 = Busy
Bits 22-16 = 7-bits ATB ID which identifies the source of the
trace data.
Bits 15-10 = Always 0
Bits 9:8 = TSPrescale = Time Stamp Prescaler
Bits 7-5 = Reserved
ITM trace control
Bit 4 = SWOENA = Enable SWV behavior (to clock the
timestamp counter by the SWV clock).
Bit 3 = DWTENA: Enable the DWT Stimulus
Bit 2 = SYNCENA: this bit must be to 1 to enable the DWT to
generate synchronization triggers so that the TPIU can then
emit the synchronization packets.
Bit 1 = TSENA (Timestamp Enable)
Bit 0 = ITMENA: Global Enable Bit of the ITM
Bit 3: mask to enable tracing ports31:24
Bit 2: mask to enable tracing ports23:16
ITM trace privilege
Bit 1: mask to enable tracing ports15:8
Bit 0: mask to enable tracing ports7:0
Each bit enables the corresponding Stimulus port to generate
ITM trace enable
trace.
Stimulus port
Write the 32-bits data on the selected Stimulus Port (32
registers 0-31
available) to be traced out.
register)
RM0366 Rev 5
Details
and
Section 28.15.3: Debug MCU
Debug support (DBG)
853/874
863

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