Interrupts and events
Bits 31:1 Reserved, must be kept at reset value.
Note:
The external wake-up lines are edge-triggered. No glitches must be generated on these
lines. If a rising edge on an external interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
11.3.10
Falling trigger selection register (EXTI_FTSR2)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Note:
The external wake-up lines are edge-triggered. No glitches must be generated on these
lines. If a falling edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.r
11.3.11
Software interrupt event register (EXTI_SWIER2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
190/874
Bit 0 TRx: Rising trigger event configuration bit of line x (x = 32)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 0 TRx: Falling trigger event configuration bit of line x (x = 32)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
RM0366 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
RM0366
17
16
Res.
Res.
1
0
Res.
TR32
rw
17
16
Res.
Res.
1
0
SWIER
Res.
32
rw
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