ST STM32F301 6 Series Reference Manual page 595

RM0366
23 Independent watchdog (IWDG)
23.1 Introduction
The devices feature an embedded watchdog peripheral (IWDG) that offers a combination of
high safety level, timing accuracy, and flexibility of use. This peripheral detects and solves
malfunctions due to software failure, and triggers a system reset when the counter reaches
a given timeout value.
The independent watchdog is clocked by its own dedicated low-speed clock (LSI), and stays
active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to
window watchdog
23.2 IWDG main features
•
Free-running downcounter
•
Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
•
Conditional reset
–
–
23.3 IWDG functional description
23.3.1 IWDG block diagram
Figure 244
V
CORE
Prescaler register
LSI
V voltage domain
DD
1. The register interface is located in the CORE voltage domain. The watchdog function is located in the V
voltage domain, still functional in Stop and Standby modes.
(WWDG).
Reset (if watchdog is activated) when the downcounter value becomes lower than
0x000
Reset (if watchdog is activated) if the downcounter is reloaded outside the window
shows the functional blocks of the independent watchdog module.
Figure 244. Independent watchdog block diagram
Status register
IWDG_PR IWDG_SR
8-bit
prescaler
Reload register
IWDG_RLR
12-bit reload value
12-bit downcounter
RM0366 Rev 5
Independent watchdog (IWDG)
Section 22: System
Key register
IWDG_KR
IWDG reset
DD
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