ST STM32F301 6 Series Reference Manual page 114

Reset and clock control (RCC)
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: COMP and SYSCFG clock enable.
Set and cleared by software.
0: SYSCFG clock disabled
1: SYSCFG clock enabled
7.4.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word, and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28
I2C3 DAC1 PWR
Res.
EN EN EN
rw rw
15 14 13 12
SPI3 SPI2
Res. Res.
EN EN
rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 I2C3EN: I2C3 clock enable (only in STM32F318x8 devices)
Set and cleared by software.
Bit 29 DAC1EN: DAC1 interface clock enable
Set and cleared by software.
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27 26 25
Res. Res. Res.
11 10 9
WWD
Res. Res.
GEN
rw
0: I2C3 clock disabled
1: I2C3 clock enabled
0: DAC1 interface clock disabled
1: DAC1 interface clock enabled
24 23 22 21
I2C2 I2C1
Res Res.
EN EN
rw rw
8 7 6 5
Res. Res. Res. Res
RM0366 Rev 5
20 19 18
USART3
Res. Res.
EN
rw
4 3 2
TIM6EN Res. Res.
rw
RM0366
17 16
USART2
Res.
EN
rw
1 0
TIM2
Res.
EN
rw