ST STM32F301 6 Series Reference Manual page 62

Embedded flash memory
3.5.7 Option byte register (FLASH_OBR)
Address offset 0x1C
Reset value: 0xXXXX XX0X
It contains the level protection notifications, error during load of option bytes and user
options.
The reset value of this register depends on the value programmed in the option byte and the
OPTERR bit reset value depends on the comparison of the option byte and its complement
during the option byte loading phase.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:24 Data1
Bits 23:16 Data0
Bits 15:8 OBR: User Option Byte
62/874
r r r r r r
Bit 15: Reserved, must be kept at reset value.
Bit 14: Reserved, must be kept at reset value.
Bit 13: VDDA_MONITOR
Bit 12: nBOOT1
Bit 11: Reserved, must be kept at reset value.
Bit 10: nRST_STDBY
Bit 9: nRST_STOP
Bit 8: WDG_SW
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 RDPRT[1:0]: Read protection Level status
00: Read protection Level 0 is enabled (ST production set up)
01: Read protection Level 1 is enabled
10: Reserved
11: Read protection Level 2 is enabled
Note: These bits are read-only.
Bit 0 OPTERR: Option byte Load error
When set, this indicates that the loaded option byte and its complement do not
match. The corresponding byte and its complement are read as 0xFF in the
FLASH_OBR or FLASH_WRPR register.
Note: This bit is read-only.
r r r r r
RM0366 Rev 5
9 8 7 6 5 4
r r r
RM0366
3 2 1 0
r r r