ST STM32F301 6 Series Reference Manual page 184

Interrupts and events
Bits 29:28 Reserved, must be kept at reset value.
Bits 25:22 MRx: Interrupt Mask on external/internal line x (x = 25 to 22)
Bits 20:19 MRx: Interrupt Mask on external/internal line x (x = 20 to 19)
Bits 17:0 MRx: Interrupt Mask on external/internal line x (x = 17 to 0)
Note: The reset value for the internal lines (23, 24, 25, 26, 27 and 28) is set to '1' to enable the
interrupt by default.
11.3.2 Event mask register (EXTI_EMR1)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. MR30 Res. Res.
rw
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 29:28 Reserved, must be kept at reset value.
184/874
Bit 31 Reserved, must be kept at reset value.
Bit 30 MRx: Interrupt Mask on external/internal line x (x = 30)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 29 Reserved, must be kept at reset value.
Bit 27 MRx: Interrupt Mask on external/internal line x (x = 27)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 26 Reserved, must be kept at reset value.
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 21 Reserved, must be kept at reset value.
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 18 Reserved, must be kept at reset value.
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
28 27 26 25
Res. Res. MR25
rw
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 MRx: Event mask on external/internal line x (x = 30)
0: Event request from Line x is masked
1: Event request from Line x is not masked
24 23 22
Res. MR23 MR22 Res.
rw rw
8 7 6
MR8 MR7 MR6 MR5
rw rw rw
RM0366 Rev 5
21 20 19 18
MR20 MR19 Res.
rw rw
5 4 3 2
MR4 MR3 MR2
rw rw rw rw
RM0366
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw