ST STM32F301 6 Series Reference Manual page 108

Reset and clock control (RCC)
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYE is set.
Cleared by software setting the PLLRDYC bit.
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYE is set.
Cleared by software setting the HSERDYC bit.
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYE is set in a response to
setting the HSION (refer to
HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no
interrupt is generated.
Cleared by software setting the HSIRDYC bit.
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYE is set.
Cleared by software setting the LSERDYC bit.
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYE is set.
Cleared by software setting the LSIRDYC bit.
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0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
Clock control register (RCC_CR)). When HSION is not set but the
RM0366 Rev 5
RM0366