ST STM32F301 6 Series Reference Manual page 526

General-purpose timers (TIM15/TIM16/TIM17)
TRGI
Counter
Output
19.4.17 UIF bit remapping
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows both
the counter value and a potential roll-over condition signaled by the UIFCPY flag, to be
atomically read. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
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Figure 226. Retriggerable one pulse mode
RM0366 Rev 5
RM0366
MS33106V2