ST STM32F301 6 Series Reference Manual page 156

Direct memory access controller (DMA)
10.4 DMA functional description
10.4.1 DMA block diagram
The DMA block diagram is shown in the figure below.
Cortex-M4
DMA
Ch.1
Ch.2
Ch.7
The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.
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Figure 21. DMA block diagram
ICode
DCode
System
DMA
CRC
AHB System bus
Reset and clock control
(RCC)
DMA request
DMA request
RM0366 Rev 5
FLITF Flash
DCode SRAM (40K)
GPIOA, B, C, D, F
ADC 1
TS
Bridge 2
Bridge 1
TIM15
TIM16
TIM17
RM0366
APB2
USART1
SPI/I2S
APB1
TIM1
SYSCFG
DAC1_CH1 TIM2
USART2 TIM6
USART3
I2C1
I2C2
I2C3
MS32688V2