ST STM32F301 6 Series Reference Manual page 590

System window watchdog (WWDG)
22.3.1 WWDG block diagram
pclk
22.3.2 Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.
22.3.3 Controlling the down-counter
This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value,
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 243). The
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
or equal to the window register value, and greater than 0x3F.
window watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
22.3.4 How to program the watchdog timeout
Use the formula in
Warning:
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Figure 242. Watchdog block diagram
Register interface
W[6:0]
WWDG_CFR
WWDG_SR
readback
WWDG_CR
preload
7-bit down-counter (CNT)
WDGTB
÷ 4096 ÷ 2
WWDG configuration register (WWDG_CFR)
Figure 243 to calculate the WWDG timeout.
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
CMP = 1 when
T[6:0] > W[6:0]
Write to
WWDG_CR
= 0x40 ?
cnt_out
RM0366 Rev 5
WWDG
WDGA
T6
EWI
EWIF
contains the high limit of the
Figure 243 describes the
RM0366
wwdg_out_rst
wwdg_it
MS47214V2