ST STM32F301 6 Series Reference Manual page 185

RM0366
Bits 25:22 MRx: Event Mask on external/internal line x (x = 25 to 22)
Bits 20:19 MRx: Event Mask on external/internal line x (x = 20 to 19)
Bits 17:0 MRx: Event Mask on external/internal line x (x = 17 to 0)
11.3.3 Rising trigger selection register (EXTI_RTSR1)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. TR30 Res. Res.
rw
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 29:23 Reserved, must be kept at reset value.
Bit 27 MRx: Event Mask on external/internal line x (x = 27)
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bit 26 Reserved, must be kept at reset value.
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 24 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 18 Reserved, must be kept at reset value.
0: Event request from Line x is masked
1: Event request from Line x is not masked
28 27 26 25
Res. Res. Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 TRx: Rising trigger event configuration bit of line x (x = 30)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bit 22 TRx: Rising trigger event configuration bit of line x (x = 22)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bit 21 Reserved, must be kept at reset value.
24 23 22
Res. Res. TR22 Res.
rw
8 7 6
TR8 TR7 TR6
rw rw rw
RM0366 Rev 5
Interrupts and events
21 20 19 18
TR20 TR19 Res.
rw rw
5 4 3 2
TR5 TR4 TR3 TR2
rw rw rw rw
17 16
TR17 TR16
rw rw
1 0
TR1 TR0
rw rw
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