ST STM32F301 6 Series Reference Manual page 706

Inter-integrated circuit interface (I2C)
25.9.7 I2C interrupt and status register (I2C_ISR)
Address offset: 0x18
Reset value: 0x0000 0001
Access: no wait states
31 30 29
Res. Res. Res. Res.
15 14 13
TIMEO
BUSY Res. ALERT
r r
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:17 ADDCODE[6:0]: Address match code (target mode)
Bit 16 DIR: Transfer direction (target mode)
Bit 15 BUSY: Bus busy
Bit 14 Reserved, must be kept at reset value.
Bit 13 ALERT: SMBus alert
Note: This bit is cleared by hardware when PE = 0.
Bit 12 TIMEOUT: Timeout or t
Note: This bit is cleared by hardware when PE = 0.
Bit 11 PECERR: PEC error in reception
Note: This bit is cleared by hardware when PE = 0.
Bit 10 OVR: Overrun/underrun (target mode)
Note: This bit is cleared by hardware when PE = 0.
706/874
28 27 26 25
Res. Res. Res.
12 11 10 9
PECER
OVR ARLO
UT R
r r r r
These bits are updated with the received address when an address match event occurs
(ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed
by the two MSBs of the address.
This flag is updated when an address match event occurs (ADDR = 1).
0: Write transfer, target enters receiver mode.
1: Read transfer, target enters transmitter mode.
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected, and cleared by hardware when a STOP condition is
detected, or when PE = 0.
This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1
and an SMBALERT# event (falling edge) is detected on SMBA pin. It is cleared by software
by setting the ALERTCF bit.
LOW
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
This flag is set by hardware in target mode with NOSTRETCH = 1, when an
overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.
24 23 22
Res.
r r
8 7 6
BERR TCR TC STOPF NACKF ADDR
r r r
detection flag
RM0366 Rev 5
21 20 19 18
ADDCODE[6:0]
r r r r
5 4 3 2
RXNE
r r r r
RM0366
17 16
DIR
r r
1 0
TXIS TXE
rs rs