ST STM32F301 6 Series Reference Manual page 187

RM0366
Note: The external wake-up lines are edge-triggered. No glitches must be generated on these
lines. If a falling edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
11.3.5 Software interrupt event register (EXTI_SWIER1)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
SWIER
Res. Res. Res.
30
rw
15 14 13
SWIER SWIER SWIER SWIER
15 14 13
rw rw rw
Bits 29:23 Reserved, must be kept at reset value.
Bits 20:19 SWIERx: Software interrupt on line x (x = 22 to 19)
Bits 17:0 SWIERx: Software interrupt on line x (x = 17 to 0)
28 27 26 25
Res. Res. Res.
12 11 10 9
SWIER SWIER SWIER
12 11 10 9
rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 SWIERx: Software interrupt on line x (x = 30)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by
writing a '1' into the bit).
Bit 22 SWIERx: Software interrupt on line x (x = 22)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
into the bit).
Bit 21 Reserved, must be kept at reset value.
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
into the bit).
Bit 18 Reserved, must be kept at reset value.
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
into the bit).
24 23 22
SWIER
Res. Res. Res.
22
rw
8 7 6
SWIER SWIER SWIER SWIER
8 7 6
rw rw rw
RM0366 Rev 5
Interrupts and events
21 20 19 18
SWIER SWIER
Res.
20 19
rw rw
5 4 3 2
SWIER SWIER SWIER
5 4 3 2
rw rw rw rw
17 16
SWIER SWIER
17 16
rw rw
1 0
SWIER SWIER
1 0
rw rw
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