ST STM32F301 6 Series Reference Manual page 274

Analog-to-digital converters (ADC)
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define the ADC clock scheme (which is common
to both master and slave ADCs):
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of
a conversion.
Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0,
Bits 15:0 Reserved, must be kept at reset value.
12.7 ADC register map
The following table summarizes the ADC registers.
Offset
0x000 - 0x04C
0x050 - 0x0FC
0x100 - 0x14C
0x118 - 0x1FC
0x200 - 0x24C
0x250 - 0x2FC
0x300 - 0x308
1. The gray color is used for reserved memory addresses.
Table 43. ADC register map and reset values for each ADC (offset=0x000
Register name
Offset
reset value
ADCx_ISR
0x00
Reset value
ADCx_IER
0x04
Reset value
274/874
00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to
Section 7: Reset and clock control
01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB
clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock
has a 50% duty cycle.
10: HCLK/2 (Synchronous clock mode)
11: HCLK/4 (Synchronous clock mode)
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Table 42. ADC global register map
Master and slave ADCs common registers (ADC1)
for master ADC, 0x100 for slave ADC, x=1)
(RCC))
Register
Master ADC1
Reserved
Reserved
Reserved
Reserved
Reserved
RM0366 Rev 5
(1)
0 0 0 0 0 0
0 0 0 0 0 0
RM0366
0 0 0 0 0
0 0 0 0 0