ST STM32F301 6 Series Reference Manual page 811

RM0366
Figure 323. I
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in
Figure 324. Example of 16-bit data frame extended to 32-bit channel frame
For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send.
This takes place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
Figure 322. Receiving 0x8EAA33
First read to Data register
0x8EAA
2
S Philips standard (16-bit extended to 32-bit packet frame)
CK
WS
Transmission
16-bit data
SD
MSB
Channel left 32-bit
Figure 324 is required.
Second read to Data register
0x33XX
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
Reception
16-bit remaining 0 forced
LSB
Only one access to SPIx_DR
0x76A3
RM0366 Rev 5
MS19594V1
Channel right
MS19599V1
MS19595V1
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