ST STM32F301 6 Series Reference Manual page 79

RM0366
Reset
6.2.2 Programmable voltage detector (PVD)
User can use the PVD to monitor the V
selected by the PLS[2:0] bits in the
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the
is higher or lower than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling
edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior
that is, if the EXTI line 16 is configured to rising edge sensitivity, the interrupt is generated
when V
DD
emergency shutdown tasks.
Figure 8. Power on reset/power down reset waveform
V DD /V DDA
POR
Power control/status register
drops below the PVD threshold. As an example the service routine could perform
40 mV
hysteresis
power supply by comparing it to a threshold
DD
Power control register
RM0366 Rev 5
Power control (PWR)
PDR
(PWR_CR).
(PWR_CSR), to indicate if V
MS19669V1
DD
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