ST STM32F301 6 Series Reference Manual page 710

Inter-integrated circuit interface (I2C)
25.9.11 I2C transmit data register (I2C_TXDR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait states
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TXDATA[7:0]: 8-bit transmit data
Note: These bits can be written only when TXE = 1.
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Data byte to be transmitted to the I²C-bus
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0366 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
TXDATA[7:0]
rw rw rw rw
RM0366
17 16
Res. Res.
1 0
rw rw