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Power control (PWR)
6.4.2
Power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wake-up from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
88/874
Bit 2 CWUF: Clear wakeup flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
Bit 1 PDDS: Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status
depends on the LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res
EWUP2 EWUP1
rw
Bit 9 EWUP2: Enable WKUP2 pin
This bit is set and cleared by software.
0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does
not wakeup the device from Standby mode.
1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull
down configuration (rising edge on WKUP2 pin wakes-up the system from
Standby mode).
Note: This bit is reset by a system Reset.
Bit 8 EWUP1: Enable WKUP1 pin
This bit is set and cleared by software.
0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does
not wakeup the device from Standby mode.
1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull
down configuration (rising edge on WKUP1 pin wakes-up the system from
Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:4 Reserved, must be kept at reset value.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
rw
RM0366 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
VREFIN
Res.
PVDO
TRDYF
r
r
RM0366
17
16
Res.
Res.
1
0
SBF
WUF
r
r
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