ST STM32F301 6 Series Reference Manual page 721

RM0366
When no transmission is taking place, a write instruction to the USART_TDR register places
the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data in the USART_TDR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see Figure 279: TC/TXE behavior when
Idle preamble
TX line
TXE flag
USART_DR F1
TC flag
Software
Software waits until TXE=1
enables the
and writes F2 into DR
USART
Software waits until TXE=1
and writes F1 into DR
Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bits (see
If a '1' is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the TXE
flag assertion before setting the SBKRQ bit.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
26.5.3 USART receiver
The USART can receive data words of either 7, 8 or 9 bits depending on the M bits in the
USART_CR1 register.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Figure 279. TC/TXE behavior when transmitting
Frame 1
Set by hardware
cleared by software
F2
Software waits until
TXE=1 and writes
F3 into DR
Figure 277).
RM0366 Rev 5
transmitting).
Frame 2
Set by hardware
cleared by software
F3
TC is not set TC is not set
because TXE=0 because TXE=0
Software waits until TC=1
Frame 3
Set by hardware
Set by hardware
TC is set
because TXE=1
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