ST STM32F301 6 Series Reference Manual page 817

RM0366
27.7.5 Clock generator
2
The I S bit rate determines the data flow on the I
frequency.
2
I S bit rate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bit rate = 16 × 2 × f
2
It is: I S bit rate = 32 x 2 x f
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
I²SxCLK
1. Where x can be 2 or 3.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
S
if the packet length is 32-bit wide.
S
Figure 337. Audio sampling frequency definition
16-or 32-bit left
sampling point
F : audio sampling frequency
S
Figure 338. I
8-bit linear divider
+ reshaping stage
I²SDIV[7:0]
MCKOE ODD
2
S data line and the I
2
S bit rate is calculated as follows:
16-or 32-bit
right channel
channel
32- or 64-bits
F
S
2
S clock generator architecture
Divider by 4
RM0366 Rev 5
2
S clock signal
sampling point
0
0
Div2
1
1
MCKOE
MS30108V1
MCK
CK
MS30109V1
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