ST STM32F301 6 Series Reference Manual page 107

RM0366
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: No effect
1: Clear CSSF flag
0: No effect
1: Clear PLLRDYF flag
0: No effect
1: Clear HSERDYF flag
0: No effect
1: Clear HSIRDYF flag
0: No effect
1: LSERDYF cleared
0: No effect
1: LSIRDYF cleared
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
RM0366 Rev 5
Reset and clock control (RCC)
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