ST STM32F301 6 Series Reference Manual page 99

RM0366
7.2.11 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
7.2.12 I2S clock
The I2S clock can be either the System clock or an external clock provided on I2S_CKIN
pin. The selection of the I2S clock source is performed using bit 23 (I2SSRC) of
RCC_CFGR register.
7.2.13 Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 5 clock signals can be selected as the MCO
clock.
•
LSI
•
LSE
•
SYSCLK
•
HSI
•
HSE
•
PLL clock not divided by 2 (using the PLLNODIV bit in RCC_CFGR register)
The selection is controlled by the MCO[2:0] bits in the
(RCC_CFGR). Furthermore, the MCO frequency can be reduced by a configurable binary
divider controlled by the MCOPRE[2:0] bits of the clock configuration register (RCC_CFGR).
7.2.14 Internal/external clock measurement with TIM16
It is possible to indirectly measure the frequency of all on-board clock sources by means of
the TIM16 channel 1 input capture. As represented on
Figure 13. Frequency measurement with TIM16 in capture mode
TI1_RMP[1:0]
GPIO
RTCCLK
HSE/32
MCO
RM0366 Rev 5
Reset and clock control (RCC)
Clock configuration register
Figure 13.
TIM16
TI1
MS30477V1
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