ST STM32F301 6 Series Reference Manual page 654

Inter-integrated circuit interface (I2C)
When the SCL falling edge is internally detected, the delay
) is inserted before sending SDA output:
t
HD;DAT
t = SDADEL x t
SDADEL
The total SDA output delay is:
t + {[SDADEL x (PRESC + 1) + 1] x t
SYNC1
The t
SYNC1
•
SCL falling slope
•
input delay t
•
input delay t
• delay due to SCL synchronization to I2CCLK clock (two to three I2CCLK periods)
To bridge the undefined region of the SCL falling edge, the user must set SDADEL[3:0] so
as to fulfill the following condition:
{t + t
f(max)
SDADEL ≤ {t
654/874
Figure 248. Setup and hold timings
SCL falling edge internal
detection
SCL
SDA
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.
SCL
SDA
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output.
+ t
PRESC I2CCLK
duration depends upon:
< t < t
AF(min) AF
= DNF t
x
DNF I2CCLK
- t - [(DNF + 3) x t
HD;DAT(min) AF(min)
- t
HD;DAT (max) AF(max)
DATA HOLD TIME
t
SDADEL: SCL stretched low by the I2C
SYNC1
SDA output delay
t
HD;DAT
DATA SETUP TIME
SCLDEL
SCL stretched low by the I2C
t
SU;STA
, where
t = (PRESC + 1) x t
PRESC
}
I2CCLK
introduced by the analog filter (if enabled)
AF(max)
introduced by the digital filter (if enabled)
]} / {(PRESC + 1) x t
I2CCLK
- [(DNF + 4) x t ]} / {(PRESC + 1) x t
I2CCLK
RM0366 Rev 5
(impacting the hold time
t
SDADEL
.
I2CCLK
} ≤ SDADEL
I2CCLK
}
I2CCLK
RM0366
MSv40108V1