ST STM32F301 6 Series Reference Manual page 112

Reset and clock control (RCC)
Bits 31:30 Reserved, must be kept at reset value.
Bit 28 ADC1EN: ADC1
Set and reset by software.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 TSCEN: Touch sensing controller clock enable
Set and cleared by software.
Bit 23 Reserved, must be kept at reset value.
Bit 22 GPIOFEN: I/O port F clock enable
Set and cleared by software.
Bit 21 Reserved, must be kept at reset value.
Bit 20 GPIODEN: I/O port D clock enable
Set and cleared by software.
Bit 19 GPIOCEN: I/O port C clock enable
Set and cleared by software.
Bit 18 GPIOBEN: I/O port B clock enable
Set and cleared by software.
Bit 17 GPIOAEN: I/O port A clock enable
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during Sleep mode.
Bit 3 Reserved, must be kept at reset value.
112/874
0: ADC1 clock disabled
1: ADC1 clock enabled
0: TSC clock disabled
1: TSC clock enabled
0: I/O port F clock disabled
1: I/O port F clock enabled
0: I/O port D clock disabled
1: I/O port D clock enabled
0: I/O port C clock disabled
1: I/O port C clock enabled
0: I/O port B clock disabled
1: I/O port B clock enabled
Set and cleared by software.
0: I/O port A clock disabled
1: I/O port A clock enabled
0: CRC clock disabled
1: CRC clock enabled
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
RM0366 Rev 5
RM0366