ST STM32F301 6 Series Reference Manual page 124

Reset and clock control (RCC)
7.4.14 RCC register map
Offset Register
RCC_CR
0x00
Reset value
RCC_CFGR
0x04
Reset value
RCC_CIR
0x08
Reset value
RCC_
APB2RSTR
0x0C
Reset value
RCC_
APB1RSTR
0x010
Reset value
RCC_AHBENR
0x14
Reset value
RCC_APB2ENR
0x18
Reset value
RCC_APB1ENR
0x1C
Reset value
RCC_BDCR
0x20
Reset value
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Table 19. RCC register map and reset values
0 0
MCO
[2:0]
0 0 0 0 0 0 0 0
0
0 0 0
0 0
0 0 0
0 0 0 0 x x
PLLMUL
[3:0]
0 0 0 0 0 0
0 0 0 0 0
0 0 0
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0 0 0 0 0
0 0
RM0366 Rev 5
HSICAL[7:0] HSITRIM[4:0]
x x x x x x 1 0 0
PPRE2 PPRE1
HPRE[3:0]
[2:0] [2:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0
0
0
0 0
0
RTC
SEL
[1:0]
0 0
RM0366
0 0 1 1
SWS SW
[1:0] [1:0]
0 0 0 0 0
0 0 0 0 0
0
0 0
1 1 0
0
0 0
LSE
DRV
[1:0]
1 1 0 0 0