ST STM32F301 6 Series Reference Manual page 223

RM0366
P2: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0)
P3: sequence of 1 conversion, software trigger (JEXTEN = 0x0)
P4: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0)
Queue of context: Starting the ADC with an empty queue
The following procedure must be followed to start ADC operation with an empty queue, in
case the first context is not known at the time the ADC is initialized. This procedure is only
applicable when JQM bit is reset:
5. Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software
conversion)
6. Set JADSTART
7. Set JADSTP
8. Wait until JADSTART is reset
9. Set JADSTART.
12.3.22 Programmable resolution (RES) - fast conversion mode
It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control
bits RES[1:0].
format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to
RES
(bits)
12
10
8
6
12.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADCx_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADCx_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADCx_JDRy
register.
Figure 53, Figure
Table 36.
Table 36. T
T
SAR
(ADC clock cycles)
12.5 ADC clock cycles 173.6 ns
10.5 ADC clock cycles 145.8 ns
8.5 ADC clock cycles
6.5 ADC clock cycles
54, Figure 55 and Figure 56
timings depending on resolution
SAR
T
ADC
T (ns) at
SAR
(with Sampling Time=
F =72 MHz
ADC
1.5 ADC clock cycles)
14 ADC clock cycles
12 ADC clock cycles
118.0 ns 10 ADC clock cycles
90.3 ns 8 ADC clock cycles
RM0366 Rev 5
Analog-to-digital converters (ADC)
show the conversion result
(ADC clock cycles)
194.4 ns
166.7 ns
138.9 ns
111.1 ns
T (ns) at
ADC
F =72 MHz
ADC
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